The present invention generally relates to semiconductor-on-insulator (SOI) integrated circuits and, more particularly, to an SOI chip having an active layer with areas made from different materials to support the fabrication of multiple threshold voltage MOSFETs and a method of making the SOI chip.
Traditional semiconductor-on-insulator (SOI) integrated circuits typically have a silicon substrate having a buried oxide (BOX) layer disposed thereon. A silicon active layer is disposed on the BOX layer. Within the active layer, active devices, such as transistors, are formed in active regions. The size and placement of the active regions are defined by isolation regions. As a result of this arrangement, the active devices are isolated from the substrate by the BOX layer. More specifically, a body region of each SOI transistor does not have body contacts and is therefore xe2x80x9cfloating.xe2x80x9d
SOI chips offer potential advantages over bulk chips for the fabrication of high performance integrated circuits for digital circuitry. Such digital circuitry is typically made from partially-depleted metal oxide semiconductor field effect transistors (MOSFETs). In such circuits, dielectric isolation and reduction of parasitic capacitance improve circuit performance, and virtually eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and the packing density greatly increased.
However, there exists a need in the art to fabricate devices having differing electrical characteristics on a single SOI chip.
According to one aspect of the invention, the invention is a semiconductor-on-insulator (SOI) chip. The SOI chip includes a substrate; a buried oxide (BOX) layer disposed on the substrate; an active layer disposed on the BOX layer, the active layer having a first area made from silicon and a second area made from silicon-germanium; a first device fabricated in the first area of the active layer and having a silicon channel and a first threshold voltage; and a second device fabricated in the second area of the active layer and having a silicon-germanium channel and a second threshold voltage differing from the first threshold voltage.
According to another aspect of the invention the invention is a semiconductor-on-insulator (SOI) chip. The SOI chip includes a substrate; a buried oxide (BOX) layer disposed on the substrate; an active layer disposed on the BOX layer, the active layer having a first area made from silicon-germanium, the first area of silicon-germanium having a first atomic concentration of silicon and a first atomic concentration of germanium, and a second area made from silicon-germanium, the second area of silicon-germanium having a second atomic concentration of silicon differing from the first atomic concentration of silicon and a second atomic concentration of germanium differing from the first atomic concentration of germanium; a first device fabricated in the first area of the active layer and having a silicon-germanium channel and a first threshold voltage; and a second device fabricated in the second area of the active layer and having a silicon-germanium channel and a second threshold voltage differing from the first threshold voltage.
According to yet another aspect of the invention, the invention is a method of fabricating a semiconductor-on-insulator (SOI) chip comprising the steps of: providing a wafer of SOI material, the wafer of SOI material having a silicon layer disposed on a buried oxide (BOX) layer, the BOX layer disposed on a substrate; implanting germanium into a portion of the silicon layer to form an active layer having a first area made from silicon and a second area made from silicon-germanium; forming a first device in the first area of the active layer, the first device having a silicon channel and a first threshold voltage; and forming a second device in the second area of the active layer, the second device having a silicon-germanium channel and a second threshold voltage differing from the first threshold voltage.
These and further features of the present invention will be apparent with reference to the following description and drawings, wherein:
FIG. 1 is a cross-section of a semiconductor-on-insulator (SOI) chip having an active layer to support the fabrication of devices with differing electrical characteristics;
FIG. 2 is a flowchart of a method for fabricating the SOI chip; and
FIGS. 3A through 3D are cross-sections of the SOI chip in various stages of manufacture.